`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/04 11:00:03
// Design Name: 
// Module Name: diffe_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module diffe_sim();

    reg clk = 0;
    reg wen = 0;
    reg clrn = 0;
    reg d = 0;
    wire q;
    
    dffe UUT(.clk(clk), .clrn(clrn), .d(d), .wen(wen), .q(q));
    
    always #5 begin clk = ~clk; end
    initial begin
        #2 begin d = 1; clrn = 1; end  // WRITE
        #10 begin wen = 1; d = 0; end  // KEEP
        #10 begin d = 1; wen = 0 ; clrn = 0; end  // ASYNC SETZ
        #30 $finish;
    end

endmodule
